CS 362 Introduction to Computer Architecture

Loyola University Chicago

Fall 2022

Summary

  • This is an advanced course that teaches how a computer works at a hardware level.
  • The schedule on this page lists the topics we will cover by date.

Required Materials

  • Laptops will be required in class. Please bring your laptop to class every day. We'll be using them for labs. Minimum system requirements:
    • 8GB RAM
    • Intel/AMD CPU
  • Textbook: Computer Organization and Design: The Hardware-Software Interface

Office Hours

  • Doyle 309
  • Tuesday: Noon - 1PM
  • Or by appointment

Labs

  • Thursday: 4PM - 6PM
  • Doyle 314

Grading

  • Treat this course like a job where you are trying to get promoted. If you show up and do your work, you will get a good grade.
  • No partial credit for code that does not compile.
    • Homework: 20 %
    • Participation: 10 %
    • Progress: 10 %
    • Checkins & Quizzes: 20 %
    • Project: 40 %
    Percentage Letter Grade
    91+ A
    89-90 A-
    87-88 B+
    77-86 B
    75-76 B-
    73-74 C+
    62-72 C
    60-61 C-
    50-59 D
    Below 50 F

Scheduling Conflicts

  • If you have a (legitimate) scheduling conflict with a quiz or exam, it is possible to schedule a makeup session. You must let me know at least two weeks prior to the quiz/exam date. Legitimate scheduling conflicts include religious observances.
  • LUC's academic calendar can be found here.

Mandatory Reporter Statment

  • Each faculty and staff member at Loyola University Chicago is required to report any incidents of gender-based misconduct that they are made aware of, even if it happened in the past. Gender-based misconduct includes discrimination based on actual or perceived sex, sexual orientation, gender expression or identity, or pregnancy or parenting status; dating and domestic violence; sexual misconduct (including sexual assault, sexual harassment, and sexual exploitation); and stalking.

Tools

Programming Resources

Collaboration

  • Students are expected to write their own code for homework assignments. No copying or code sharing is allowed. Copying code from the Internet is also not allowed.

Course Schedule

Tenative

Date Topic Details
Wed 08/31 Intro; Review of Combinatorial Logic Homework: Flip Flops Homework
Homework 1 Assigned
Fri 09/02 Review of Sequential Logic
Wed 09/07 Performance: Speedup, Benchmarks, MIPS, the Iron Law, Amdahl's Law Further Reading:
  • Patterson & Hennesy Chapter 1.6
Fri 09/09 Instruction Set Intro
Further Reading:
  • Patterson & Hennesy 2.1-2.3
Wed 09/14 Machine Code, Stacks, and Endianness Homework 1 Due
Homework 2: 2-1/4-1 Muxes and Full Adder in Verilog
Further Reading:
  • Patterson & Hennesy 2.5
Fri 09/16 Verilog Tutorial Further Reading:
  • Patterson & Hennesy A.2-A.4
Wed 09/21 Verilog Tutorial Video: Synthesizing a Simple Design on the DE10-Lite
Fri 09/23 Ripple Carry and Carry Select Adders Homework 2 Due
Homework 3: Implement (1) 32-bit Barrel Shifter, (2) an ALU & (3) Register File in Verilog
Wed 09/28 Carry Lookahead Adder Further Reading:
  • Patterson & Hennesy A.6
Fri 09/30 ALUs Further Reading:
  • Patterson & Hennesy A.5
Wed 10/05 Single-Cycle Processor Datapath Homework 3 Due
Start working on Project Schematic Further Reading:
  • Patterson & Hennesy 4.1-4.3
Fri 10/07 Single Cycle Processor Control Path memory2c.v
Further Reading:
  • Patterson & Hennesy 4.4
Wed 10/12 Data Dependences
Fri 10/14 Project Design Review
Wed 10/19 Pipeline Datapath Further Reading:
  • Patterson & Hennesy 4.6
Fri 10/21 Pipeline Control
Wed 10/26 Pipelining: Control Dependences & Branch Delay Slot Further Reading:
  • Patterson & Hennesy 4.7-4.8
Fri 10/28 Exceptions Further Reading:
  • Patterson & Hennesy 4.9
Wed 11/02 Cache Concepts Further Reading:
  • Patterson & Hennesy 5.1-5.2
Fri 11/04 Cache Design Further Reading:
  • Patterson & Hennesy 5.3
Wed 11/09 Cache Design
Fri 11/11 Cache Performance
Wed 11/16 Phase I Demo Day Project Phase I Due
Fri 11/18 Virtual Memory Further Reading:
  • Patterson & Hennesy 5.7
Wed 11/23 Main Memory Further Reading:
  • Patterson & Hennesy A.9
Fri 11/25 I/O
Wed 11/30 Superscalar Further Reading:
Fri 12/02 Superscalar
Wed 12/07 Out of order
Fri 12/09 Booth's Algorithm for Multiplication
Wed 12/14 Floating Point
Fri 12/16 Phase II Demo Day
Wed 12/21
Fri 12/23
Wed 12/28
Fri 12/30
Wed 01/04
Fri 01/06
Wed 01/11
Fri 01/13
Wed 01/18
Fri 01/20
Wed 01/25
Fri 01/27
Wed 02/01
Fri 02/03 Phase III Demo Day